A known operational transconductance amplifier circuit structure is shown in FIG. 1. This amplifier circuit 1 is capable of supplying a rail to rail output signal OUT1. An operational transconductance amplifier circuit of this type with an inverted structure is also disclosed in CH Patent No. 689,088 (FIG. 5) for use as active polarizing means in a quartz oscillator.
The amplifier circuit of FIG. 1 includes a differential pair of PMOS transistors P3 and P4, wherein the sources of both PMOS transistors are connected to a current source 2. The current source 2, which is connected to a high potential terminal VDD of the supply voltage source, supplies a constant current I0 to the differential pair of PMOS transistors. The gate of the first PMOS input transistor P3 forms a non inverting input XOUT, while the gate of the second PMOS input transistor P4 forms an inverting input XIN of amplifier circuit 1.
The drain of the first PMOS input transistor P3 is connected to a diode connected NMOS transistor N2 of a first current mirror connected to a low potential terminal of the supply voltage source, for example, to earth. The gate of diode connected NMOS transistor N2 is connected to the gate of an identical, second NMOS transistor N1 of the first current mirror, to mirror the current passing through NMOS transistor N2 in second NMOS transistor N1. The drain of the second PMOS input transistor P4 is connected to a diode connected NMOS transistor N3 of a second current mirror connected to a low potential terminal of the supply voltage source, for example, to earth. The gate of diode connected NMOS transistor N3 is connected to the gate of an identical, second NMOS transistor N4 of the second current mirror to mirror the current passing through NMOS transistor N3 in second NMOS transistor N4.
The drain of the second NMOS transistor N4 of the second current mirror is connected to a diode connected PMOS transistor P2 of a third current mirror, which is connected to a high potential terminal VDD of the supply voltage source. The gate of this diode connected PMOS transistor P2 is connected to the gate of a second PMOS transistor P1 of the third current mirror, to mirror the current passing through diode connected PMOS transistor P2 in identical, second PMOS transistor P1. Finally, the drain of the second PMOS transistor P1 of the third current mirror is connected to the drain of the second NMOS transistor N1 of the first current mirror to define an output node for supplying an output signal OUT1.
When the voltage applied at inverting input XIN of the second PMOS transistor P4 of the differential pair is lower than the voltage applied at the non-inverting input XOUT of the first PMOS transistor P3 of the differential pair, the current I0 from current source 2 passes through the second and third current mirrors. Consequently, the level of output signal OUT1 is close to supply voltage VDD. Conversely, when the voltage applied at the non-inverting input XOUT of the first PMOS transistor P3 is lower than the voltage applied to the inverting input XIN of the second PMOS transistor P4, the current from current source 2 passes through the first current mirror. In these conditions, the level of output signal OUT1 is close to earth. However, at the conduction threshold of each PMOS transistor P3 and P4 of the differential pair, when the voltage level across each input XIN and XOUT is close, there is generally significant phase noise degradation. This phase noise is degraded, in particular, at the moment of transition of conduction between the two PMOS transistors of the differential pair with two oscillating, sinusoidal signals in phase opposition applied respectively across inverting input XIN and non-inverting input XOUT.
The current in each current mirror, which is connected to the respective PMOS transistor of the differential pair, is generally not cut off quickly during transition of conduction between the PMOS transistors of the differential pair. A non-zero current remains in the current mirror, which should normally be in a non-conductive state, which decreases the amplifier gain and allows the noise generated in the transistors or in an external circuit, such as, for example, the supply source, to vary the moment of transition randomly. This results in signal phase noise degradation. This therefore constitutes a drawback of this amplifier circuit when it is used, for example, in a frequency synthesiser, radio-frequency signal receiver, analogue-digital converter or DC-DC converter.
Reference can be made to U.S. Pat. No. 6,806,744 for a simplified embodiment of an operational transconductance amplifier (OTA). The amplifier circuit of this Patent has only one differential pair of PMOS transistors, connected to a current source, which is connected to a high potential terminal of a supply voltage source, and also to a single NMOS current mirror, which is connected to earth. A connection node between a NMOS transistor of the mirror and one of the PMOS transistors of the differential pair supplies the amplifier circuit output signal. However, with this type of structure, the output signal cannot extend rail to rail, as in the present invention. Moreover, there is no provision for avoiding phase noise degradation, which constitutes another drawback.